IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Dynamically Reconfigurable Architecture Combining Pixel-Level SIMD and Operation-Pipeline Modes for High Frame Rate Visual Processing

International Conference on Field-Programmable Technology

Author(s): N. Iwata ; S. Kagami ; K. Hashimoto
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2007
Conference Location: Kitakyushu, Japan
Conference Date: 12 December 2007
Page(s): 321 - 324
ISBN (CD): 978-1-4244-1472-7
ISBN (Paper): 978-1-4244-1471-0
DOI: 10.1109/FPT.2007.4439276
Regular:

This paper describes a new reconfigurable processor architecture specialized for high frame rate visual processing. This architecture employs a 2-D mesh processing element (PE) array in which the... View More

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