IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimal Buffering of FPGA Interconnect for Expected Delay Optimization

International Conference on Field-Programmable Technology

Author(s): Yi-Ru He ; Wai-Kei Mak
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2007
Conference Location: Kitakyushu, Japan
Conference Date: 12 December 2007
Page(s): 289 - 292
ISBN (CD): 978-1-4244-1472-7
ISBN (Paper): 978-1-4244-1471-0
DOI: 10.1109/FPT.2007.4439268
Regular:

The designers of field-programmable gate arrays (FPGAs) always devote to optimize the chip performance. The interconnect delay is a crucial determining factor of circuit performance in FPGA based... View More

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