IEEE - Institute of Electrical and Electronics Engineers, Inc. - Improving Bounds for FPGA Logic Minimization

International Conference on Field-Programmable Technology

Author(s): T. Todman ; Haofan Fu ; O. Mencer ; W. Luk
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2007
Conference Location: Kitakyushu, Japan
Conference Date: 12 December 2007
Page(s): 245 - 248
ISBN (CD): 978-1-4244-1472-7
ISBN (Paper): 978-1-4244-1471-0
DOI: 10.1109/FPT.2007.4439257
Regular:

We present a methodology for improving the bounds of combinational designs implemented on networks of lookup tables, moving them closer to the theoretical minimum. Our work effectively extends... View More

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