IEEE - Institute of Electrical and Electronics Engineers, Inc. - Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication

2007 International Symposium on System-on-Chip

Author(s): K. Heyrman ; A. Papanikolaou ; F. Catthoor ; P. Veelaert ; W. Philips
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2007
Conference Location: Tampere, Finland
Conference Date: 20 November 2007
Page(s): 1 - 4
ISBN (CD): 978-1-4244-1368-3
ISBN (Paper): 978-1-4244-1367-6
ISSN (CD): 07EX1846C
ISSN (Paper): 07EX1846
DOI: 10.1109/ISSOC.2007.4427432
Regular:

The sectioned bus is an energy-optimal architecture for system-on-chip (SoC) communication, where we save energy by consequently switching off unused bus sections on a cycle-by-cycle basis. The... View More

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