IEEE - Institute of Electrical and Electronics Engineers, Inc. - Warpage Modeling and Characterization to Simulate the Fabrication Process of Wafer-Level Adhesive Bonding

2007 32nd IEEE/CPMT International Electronic Manufacturing Technology Symposium

Author(s): Ji-hyuk Lim ; Suk-jin Ham ; Byung-gil Jeong
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: San Jose, CA, USA
Conference Date: 3 October 2007
Page(s): 298 - 302
ISBN (CD): 978-1-4244-1336-2
ISBN (Paper): 978-1-4244-1335-5
ISSN (Paper): 1089-8190
DOI: 10.1109/IEMT.2007.4417081
Regular:

Since the array of wafer-level packages formed by bonding of a cap wafer to a substrate wafer, how to well encapsulate the intricate sensor devices in wafer-level is the critical issue in the... View More

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