IEEE - Institute of Electrical and Electronics Engineers, Inc. - VLSI power wiring noise analysis using MOR method

2007 7th International Conference on ASIC Proceeding

Author(s): K. Saeki ; H. Miwa ; G. Suzuki
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 1,186 - 1,189
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415846
Regular:

Demand for techniques to reduce verification time has been increasing in recent VLSI designs using sub-micron processes. The model order reduction (MOR) method by M.Celik et al. (2002) shortens... View More

Advertisement