IEEE - Institute of Electrical and Electronics Engineers, Inc. - Threshold voltage modeling of deep-submicron double-gate fully-depleted SOI MOSFET

2007 7th International Conference on ASIC Proceeding

Author(s): Zhang Zhengfan ; Fang Jian ; Li Ruzhang ; Zhang Zhengyuan ; Li Zhaoji
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 1,154 - 1,157
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415838
Regular:

In this paper, the threshold voltage model using a quasi -2D approximation for deep submicron double-gate fully-depleted SOI PMOS devices was described by solving basic semiconductor physical... View More

Advertisement