IEEE - Institute of Electrical and Electronics Engineers, Inc. - How to process a multi million gate ASIC layout in 21 hours

2007 7th International Conference on ASIC Proceeding

Author(s): Haoxing Ren ; K. Bercaw ; T. Chadwick ; T. Guzowski ; J. Koehl ; J. Miller ; S. Urish
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 1,118 - 1,121
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415829
Regular:

This paper discusses the turn around time reduction issue for the ASIC layout design process. It reviews key technologies to reduce the runtime of several of the most time consuming design steps.... View More

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