IEEE - Institute of Electrical and Electronics Engineers, Inc. - Performance maximized interlayer via planning for 3D ICs

2007 7th International Conference on ASIC Proceeding

Author(s): Jun Lu ; Song Chen ; T. Yoshimura
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 1,096 - 1,099
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415824
Regular:

As the development of semiconductor industry, 3D IC technology is introduced for its advantages in alleviating the interconnect problem coming with decreasing feature size and increasing... View More

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