IEEE - Institute of Electrical and Electronics Engineers, Inc. - Floorplanning with constraint extraction based on interconnecting information analysis

2007 7th International Conference on ASIC Proceeding

Author(s): Jiayi Liu ; Sheqin Dong ; Xianlong Hong ; S. Goto
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 1,084 - 1,087
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415821
Regular:

After the phase of high level synthesis, a lot of design information is hidden for the floorplanning process. As a result, the floorplanning process which is only aiming at decreasing area and... View More

Advertisement