IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design theory and fabrication process integration of 65nm and 32nm Node Si vertical dual carrier field effect transistor CPU for parallel arrays of computers.

2007 7th International Conference on ASIC Proceeding

Author(s): S.G. Shen ; P.S. Xia ; L.B. Zhang ; Y.H. Yang ; G.H. Li ; R. Yang ; D.H. Huang ; C. Huang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 1,058 - 1,061
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415815
Regular:

In this paper, we present the design theory and fabrication process integration of 65 nm and 32 nm node Si and Si1-xGex vertical dual carrier field effect transistor (VDCFET)... View More

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