IEEE - Institute of Electrical and Electronics Engineers, Inc. - Array and high voltage path design for SONOS flash memory

2007 7th International Conference on ASIC Proceeding

Author(s): Dong Wu ; Liyang Pan ; Lei Sun ; Jun Zhu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 1,034 - 1,037
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415809
Regular:

A 1.8 V/3.3 V 4 Mb Embedded SONOS flash memory has been successfully developed and verified with a 0.18 mum CMOS logic compatible integrated technology, in which a reverse read array architecture... View More

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