IEEE - Institute of Electrical and Electronics Engineers, Inc. - Testing methods for integrated circuit of phase locked loops

2007 7th International Conference on ASIC Proceeding

Author(s): K.D. Feng ; A.R. Malladi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 978 - 981
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415796
Regular:

The conventional integrated circuit phase locked loop (PLL) has few output signals and offers limited testability. In an event where PLL function does not conform to the specifications, it is... View More

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