Formal verification of VHSIC Hardware Description Language (VHDL) in Field-Programmable Gate Array (FPGA) design has been discussed for many years. In this paper we provide a practical approach to do so. We present a semi-automatic way to verify FPGA VHDL software deadlocks, especially those that re...

Estimation of density and hazard rate is very important to the reliability analysis of a system. In order to estimate the density and hazard rate of a hazard rate monotonously decreasing system, a new nonparametric estimator is put forward. The estimator is based on the kernel function method and op...

A novel reconfigurable hardware system which uses both multi-DSP and FPGA to attain high performance and real-time image processing are presented. The system structure and working principle of mainly processing multi-DSP board, extended multi-DSP board are analysed. The outstanding advantage is that...

An accelerated proportional degradation hazards-odds model is proposed. It is a non-parametric model and thus has path-free and distribution-free properties, avoiding the errors caused by faulty assumptions of degradation paths or distribution of degradation measurements. It is established based on ...

Digital down converter (DDC) is the main part of the next generation high frequency (HF) radar. In order to realize the single chip integrations of digital receiver hardware in the next generation HF Radar, a new design for DDC by using FPGA is presented. Some important and practical applications ar...