IEEE - Institute of Electrical and Electronics Engineers, Inc. - Mixed bus width architecture for low cost AES VLSI design

2007 7th International Conference on ASIC Proceeding

Author(s): Yibo Fan ; Jidong Wang ; T. Ikenaga ; S. Goto
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 854 - 857
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415765
Regular:

With the increase of security problem, AES is widely used in a lot of secure systems. For some low data throughput applications, low cost design is more attractive than high speed design. In this... View More

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