IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 2.5-Gb/s half-rate clock and data recovery circuit with a digital quadricorrelator frequency detector

2007 7th International Conference on ASIC Proceeding

Author(s): Tang Shimin ; Chen Jihua ; Chen Nuxing ; Feng Yingjie
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 604 - 607
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415703
Regular:

A 2.5-Gb/s clock and data recovery (CDR) circuit, which incorporates dual loop architecture with half-rate linear phase detector and digital quadricorrelator frequency detector (DQFD) was present... View More

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