IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimum design of a fully differential 12bit 100MS/s sample and hold module with over 77dB SFDR

2007 7th International Conference on ASIC Proceeding

Author(s): Ke Liu ; Hai-gang Yang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 442 - 445
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415662
Regular:

A fully differential sample and hold module has been designed for the front-end of a pipeline ADC using 0.35 mum 2P4M CMOS technology with a power supply of 3.3 V. The key design issues include... View More

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