IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low-power CMOS folding and interpolating ADC with a fully-folding technique

2007 7th International Conference on ASIC Proceeding

Author(s): Zhen Liu ; Yuan Wang ; Song Jia ; Lijiu Ji ; Xing Zhang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 265 - 268
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415618
Regular:

A 8-bit 150 MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-folding technique is designed in a 0.35 mum standard digital CMOS process. Folding circuits are... View More

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