IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design theory and fabrication process integration of 32nm node Si, Ge and Si 1-x Ge x vertical dual carrier field effect transistor SOC for switching and communication applications

2007 7th International Conference on ASIC Proceeding

Author(s): C. Huang ; Y.H. Yang ; D.H. Huang ; Y.Z. Xu ; Y.F. Zhao ; D. Bai ; J. Xu ; D.G. Liu ; G.H. Li ; R. Yang ; P. Xu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 173 - 176
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415595
Regular:

With the announcement of Intel and IBM to provide 45 nm CPUs, the semiconductor industry has been engaged in the research and development work of 32 nm node CMOS technology. In this paper, we... View More

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