IEEE - Institute of Electrical and Electronics Engineers, Inc. - An FPGA configuration circuit used for fast and partial configuration

2007 7th International Conference on ASIC Proceeding

Author(s): Yabin Wang ; Yuan Wang ; Jinmei Lai
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 157 - 160
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415591
Regular:

An improved architecture used for FPGA's fast and partial configuration is proposed. It is designed based on a 32 bits wide data bus, which can be controlled by a set of instructions. A partial... View More

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