IEEE - Institute of Electrical and Electronics Engineers, Inc. - Power estimation technique for Reed-Muller logic circuits

2007 7th International Conference on ASIC Proceeding

Author(s): Xien Ye ; Xue Gan ; Yinshui Xia
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Guilin, China
Conference Date: 22 October 2007
Page(s): 149 - 152
ISBN (CD): 978-1-4244-1132-0
ISBN (Paper): 978-1-4244-1131-3
DOI: 10.1109/ICASIC.2007.4415589
Regular:

A power estimation technique for Reed-Muller logic circuits is proposed. Given the probability and transition density of input signals, AND/XOR gates are decomposed into a 2-input gate tree and... View More

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