IEEE - Institute of Electrical and Electronics Engineers, Inc. - Beyond 320 Mbyte/s with 2eSST and Bus Invert coding on VME64x

2007 15th IEEE-NPSS Real Time Conference

Author(s): A. Aloisio ; F. Cevenini ; R. Cicalese ; R. Giordano ; V. Izzo
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2007
Conference Location: Batavia, IL, USA
Conference Date: 29 April 2007
Page(s): 1 - 7
ISBN (CD): 978-1-4244-0867-2
ISBN (Paper): 978-1-4244-0866-5
DOI: 10.1109/RTC.2007.4382784
Regular:

The VME64x standard includes a double data rate block transfer cycle known as 2eSST. In order to achieve the maximum bandwidth, 64-bit words are exchanged in bursts across the backplane without... View More

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