IEEE - Institute of Electrical and Electronics Engineers, Inc. - Reduction of Fault Latency in Sequential Circuits by using Decomposition

2007 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems

Author(s): I. Levin ; B. Abramov ; V. Ostrovsky
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2007
Conference Location: Rome, Italy
Conference Date: 26 September 2007
Page(s): 261 - 272
ISBN (Paper): 978-0-7695-2885-4
ISSN (Paper): 1550-5774
DOI: 10.1109/DFT.2007.24
Regular:

The paper discusses a novel approach for reduction of fault detection latency in a self-checking sequential circuit. The Authors propose decomposing the finite state machine (FSM) which describes... View More

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