IEEE - Institute of Electrical and Electronics Engineers, Inc. - TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs

2007 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems

Author(s): C. Bolchini ; A. Miele ; M.D. Santambrogio
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2007
Conference Location: Rome, Italy
Conference Date: 26 September 2007
Page(s): 87 - 95
ISBN (Paper): 978-0-7695-2885-4
ISSN (Paper): 1550-5774
DOI: 10.1109/DFT.2007.25
Regular:

This paper presents the adoption of the triple modular redundancy coupled with the partial dynamic reconfiguration of field programmable gate arrays to mitigate the effects of soft errors in such... View More

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