IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Dual PFD Phase Rotating Multi-Phase PLL for 5Gbps PCI Express Gen2 Multi-Lane Serial Link Receiver in 0.13um CMOS

2007 Symposia on VLSI Technology and Circuits

Author(s): Sungjoon Kim ; Dongyun Lee ; Young-Soo Park ; Yongsam Moon ; Daeyun Shim
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2007
Conference Location: Kyoto, Japan
Conference Date: 14 June 2007
Page(s): 234 - 235
ISBN (CD): 978-4-900784-05-5
ISBN (Paper): 978-4-900784-04-8
DOI: 10.1109/VLSIC.2007.4342732
Regular:

A dual phase frequency detector phase-locked loop (PLL) architecture for multi-lane 5 Gbps serial link receiver is demonstrated using 0.13 mum CMOS. The PLL's 8 multiphase clocks can be rotated... View More

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