IEEE - Institute of Electrical and Electronics Engineers, Inc. - A four-quadrant NMOS analog multiplier

Author(s): D.C. Soo ; R.G. Meyer
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 1982
Volume: 17
Page(s): 1,174 - 1,178
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/JSSC.1982.1051877
Regular:

A four-quadrant NMOS analog multiplier, which achieves linearity better than 0.3 percent at 75 percent of full-scale swing, a bandwidth of DC to 1.5 MHz, and output noise 77 dB below full scale is... View More

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