IEEE - Institute of Electrical and Electronics Engineers, Inc. - Clock buffer and wire sizing using sequential programming

2006 Design Automation Conference

Author(s): M.R. Guthaus ; D. Sylvester ; R.B. Brown
Sponsor(s): SiCda
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: San Francisco, CA, USA
Conference Date: 24 July 2006
Page(s): 1,041 - 1,046
ISBN (Paper): 1-59593-381-6
ISSN (Paper): 0738-100X
DOI: 10.1145/1146909.1147171
Regular:

This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequential... View More

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