IEEE - Institute of Electrical and Electronics Engineers, Inc. - A reliable failure analysis methodology in analyzing the elusive gate-open failures

Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits

Author(s): N.C. Remo ; J.C.M. Fernandez
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Singapore, Singapore
Conference Date: 27 June 2005
Page Count: 5
Page(s): 185 - 189
ISBN (Paper): 0-7803-9301-5
DOI: 10.1109/IPFA.2005.1469158
Regular:

Gate-open failures are typically caused by physical disconnections within the various gate contact interfaces inside the package such as gate lead post to wire bond, die bond pad to wire bond, or... View More

Advertisement