IEEE - Institute of Electrical and Electronics Engineers, Inc. - On reducing peak current and power during test

Proceedings. IEEE Computer Society Annual Symposium on VLSI

Author(s): Wei Li ; S.M. Reddy ; I. Pomeranz
Sponsor(s): IEEE Comput. Soc. Tech. Comm. on VLSI
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Tampa, FL, USA
Conference Date: 11 May 2005
Page(s): 156 - 161
ISBN (Paper): 0-7695-2365-X
DOI: 10.1109/ISVLSI.2005.53
Regular:

This paper presents a progressive match filling (PMF) technique to reduce the peak current and power dissipation during the fast capture cycle in broadside delay fault testing. The proposed method... View More

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