IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low hardware complexity parallel turbo decoder architecture

ISCAS 2003. International Symposium on Circuits and Systems

Author(s): Zhongfeng Wang ; Yiyan Tang ; Yuke Wang
Sponsor(s): IEEE Circuits & Syst. Soc
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Bangkok, Thailand
Conference Date: 25 May 2003
Volume: 2
Page Count: 4
ISBN (Paper): 0-7803-7761-3
DOI: 10.1109/ISCAS.2003.1205885
Regular:

Turbo decoders inherently have low throughput and long latency because of iterative decoding. Parallel processing is a powerful technique for high-throughput applications but often comes with... View More

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