IEEE - Institute of Electrical and Electronics Engineers, Inc. - A hierarchical analysis methodology for chip-level power delivery with realizable model reduction

Conference of Asia and South Pacific Design Automation 2003

Author(s): Yu-Min Lee ; C. Chung-Ping Chen
Sponsor(s): IEEE Circuits & Syst. Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Kitakyushu, Japan, Japan
Conference Date: 24 January 2003
Page Count: 5
Page(s): 614 - 618
ISBN (Paper): 0-7803-7659-5
DOI: 10.1109/ASPDAC.2003.1195098
Regular:

In this paper, we propose a novel hierarchical analysis methodology to facilitate efficient chip-level power fluctuation analysis. With extreme efficiency and simplicity, our design methodology... View More

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