IEEE - Institute of Electrical and Electronics Engineers, Inc. - Automatic generation of simulation monitors from quantitative constraint formula [system-level verification]

6th Design Automation and Test in Europe (DATE 03)

Author(s): Xi Chen ; H. Hsieh ; F. Balarin ; Y. Watanabe
Sponsor(s): EDAA
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Munich, Germany, Germany
Conference Date: 7 March 2003
Page Count: 2
Page(s): 1,174 - 1,175
ISBN (Paper): 0-7695-1870-2
ISSN (Paper): 1530-1591
DOI: 10.1109/DATE.2003.1253787
Regular:

System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulation will remain an... View More

Advertisement