IEEE - Institute of Electrical and Electronics Engineers, Inc. - Improving SAT-based bounded model checking by means of BDD-based approximate traversals

6th Design Automation and Test in Europe (DATE 03)

Author(s): G. Cabodi ; S. Nocco ; S. Quer
Sponsor(s): EDAA
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Munich, Germany, Germany
Conference Date: 7 March 2003
Page Count: 6
Page(s): 898 - 903
ISBN (Paper): 0-7695-1870-2
ISSN (Paper): 1530-1591
DOI: 10.1109/DATE.2003.1253720
Regular:

Binary Decision Diagrams (BDDs) have been widely used for hardware verification since the beginning of the '90s, whereas Boolean Satisfiability (SAT) has been gaining ground more recently, with... View More

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