IEEE - Institute of Electrical and Electronics Engineers, Inc. - Scheduling and mapping of conditional task graphs for the synthesis of low power embedded systems

6th Design Automation and Test in Europe (DATE 03)

Author(s): Dong Wu ; B.M. Al-Hashimi ; P. Eles
Sponsor(s): EDAA
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Munich, Germany, Germany
Conference Date: 7 March 2003
Page Count: 6
Page(s): 90 - 95
ISBN (Paper): 0-7695-1870-2
ISSN (Paper): 1530-1591
DOI: 10.1109/DATE.2003.1253592
Regular:

This paper describes a new dynamic voltage scaling (DVS) technique for embedded systems expressed as conditional task graphs (CTGs). The idea is to identify and exploit the available worst case... View More

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