IEEE - Institute of Electrical and Electronics Engineers, Inc. - Application of look-up table approach to high-K gate dielectric MOS transistor circuits

Proceedings 16th International Conference on VLSI Design. Concurrently with the 2nd International Conference on Embedded Systems Design

Author(s): D.V. Kumar ; N.R. Mohapatra ; M.B. Patil ; V.R. Rao
Sponsor(s): VLSI Soc. India (VSI) Minstr. Commun. & Inf. Technol., Govern. India
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: New Delhi, India, India
Conference Date: 4 January 2003
Page Count: 6
Page(s): 128 - 133
ISBN (Paper): 0-7695-1868-0
ISSN (Paper): 1063-9667
DOI: 10.1109/ICVD.2003.1183126
Regular:

In this paper, we study the circuit performance issues of high-K gate dielectric MOSFETs using the Look-up Table (LUT) approach. The LUT approach is implemented in a public-domain circuit... View More

Advertisement