IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low power technology mapping for LUT based FPGA - a genetic algorithm approach

Proceedings 16th International Conference on VLSI Design. Concurrently with the 2nd International Conference on Embedded Systems Design

Author(s): R. Pandey ; S. Chattopadhyay
Sponsor(s): VLSI Soc. India (VSI) Minstr. Commun. & Inf. Technol., Govern. India
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: New Delhi, India, India
Conference Date: 4 January 2003
Page Count: 6
Page(s): 79 - 84
ISBN (Paper): 0-7695-1868-0
ISSN (Paper): 1063-9667
DOI: 10.1109/ICVD.2003.1183118
Regular:

In this paper we consider the problem of LookUp Table (LUT) based FPGA technology mapping for power minimization in combinational circuits. The problem has been previously proven to be NP-complete... View More

Advertisement