IEEE - Institute of Electrical and Electronics Engineers, Inc. - Double abstraction level heuristic power optimization for digital signal processors using GA's

Proceedings of the 46th International Midwest Symposium on Circuits and Systems

Author(s): C. Shrutisagar ; N. Sridhara Krishnan
Sponsor(s): IEEE Circuits and Syst. Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Cairo, Egypt
Conference Date: 27 December 2003
Volume: 3
ISBN (Paper): 0-7803-8294-3
ISSN (Paper): 1548-3746
DOI: 10.1109/MWSCAS.2003.1562593
Regular:

In this paper the authors explored a new approach towards optimization of dedicated reconfigurable DSP processors using a two pronged approach. At the logic level, metarules are used to abstract... View More

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