IEEE - Institute of Electrical and Electronics Engineers, Inc. - A simulation-based temporal assertion checker for PSL

Proceedings of the 46th International Midwest Symposium on Circuits and Systems

Author(s): Kai-Hui Chang ; Wei-Ting Tu ; Yi-Jong Yeh ; Sy-Yen Kuo
Sponsor(s): IEEE Circuits and Syst. Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Cairo, Egypt
Conference Date: 27 December 2003
Volume: 3
ISBN (Paper): 0-7803-8294-3
ISSN (Paper): 1548-3746
DOI: 10.1109/MWSCAS.2003.1562587
Regular:

A simulation-based temporal assertion verification engine for PSL (property specification language), called Tempral Wizard, is proposed in this paper. It is very efficient because its time and... View More

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