IEEE - Institute of Electrical and Electronics Engineers, Inc. - Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS

Author(s): Taehui Na ; Byungkyu Song ; Sara Choi ; Jung Pill Kim ; Seung H. Kang ; Seong-Ook Jung
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2019
Volume: 27
Page(s): 2,548 - 2,555
ISSN (Electronic): 1557-9999
ISSN (Paper): 1063-8210
DOI: 10.1109/TVLSI.2019.2925931
Regular:

In the design of nonvolatile memory (NVM), the sensing scheme (SS) has become a read-energy bottleneck because the required read-cell current is too large to satisfy a target read yield. This... View More

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