IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Minimum-Skew Clock Tree Synthesis Algorithm for Single Flux Quantum Logic Circuits

Author(s): Soheil Nazar Shahsavani ; Massoud Pedram
Sponsor(s): Council on Superconductivity
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2019
Volume: 29
Page(s): 1 - 13
ISSN (CD): 2378-7074
ISSN (Electronic): 1558-2515
ISSN (Paper): 1051-8223
DOI: 10.1109/TASC.2019.2943930
Regular:

This article presents a synchronous minimum-skew clock tree synthesis algorithm for single flux quantum circuits considering splitter delays and placement blockages. The proposed methodology... View More

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