IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers

Author(s): Mohammad H. Naderi ; Chulhyun Park ; Suraj Prakash ; Martin Kinyua ; Eric G. Soenen ; Jose Silva-Martinez
Sponsor(s): IEEE Circuits and Systems Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2019
Volume: 66
Page(s): 3,352 - 3,364
ISSN (Electronic): 1558-0806
ISSN (Paper): 1549-8328
DOI: 10.1109/TCSI.2019.2927383
Regular:

This paper presents a 12-bit 500 MS/s pipelined ADC fabricated in the 40 nm TSMC technology, which aims to reduce the power consumption associated with residue amplifiers and comparator cells. ADC... View More

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