IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

Author(s): Dadian Zhou ; Carlos Briseno-Vidrios ; Junning Jiang ; Chulhyun Park ; Qiyuan Liu ; Eric G. Soenen ; Martin Kinyua ; Jose Silva-Martinez
Sponsor(s): IEEE Circuits and Systems Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2019
Volume: 66
Page(s): 3,373 - 3,383
ISSN (Electronic): 1558-0806
ISSN (Paper): 1549-8328
DOI: 10.1109/TCSI.2019.2925743
Regular:

A pipeline analog-to-digital converter (ADC) with high power efficiency is implemented in this paper. The ADC architecture consists of 3.5b, 3.5b, 3.5b, and 4b sub-ADCs. For the first three... View More

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