IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic

Author(s): Daniel S. Truesdell ; Jacob Breiholz ; Sumanth Kamineni ; Ningxi Liu ; Albert Magyar ; Benton H. Calhoun
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2019
Volume: 2
Page(s): 57 - 60
ISSN (Electronic): 2573-9603
DOI: 10.1109/LSSC.2019.2938897
Regular:

This letter presents an RISC-V microprocessor implemented using a proposed scalable dynamic leakage suppression (SDLS) logic style. Together with a custom adaptive clock generator and voltage... View More

Advertisement