IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS

Author(s): Luca Bertulessi ; Saleh Karman ; Dmytro Cherniak ; Alessandro Garghetti ; Carlo Samori ; Andrea L. Lacaita ; Salvatore Levantino
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1 - 10
ISSN (Electronic): 1558-173X
ISSN (Paper): 0018-9200
DOI: 10.1109/JSSC.2019.2940332
Regular:

This article describes the implementation of a 30-GHz frequency synthesizer. The target is to reduce the gap in terms of jitter-power product that exists between millimeter-wave and RF... View More

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