IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

Author(s): Chao-Jun Shang ; Cheng-Hung Wu ; Kuen-Jong Lee ; Yu-Hsiang Chen
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2019
Conference Location: Hsinchu, Taiwan, Taiwan
Conference Date: 22 April 2019
Page(s): 1 - 4
ISBN (Electronic): 978-1-7281-0655-7
ISSN (Electronic): 2472-9124
DOI: 10.1109/VLSI-DAT.2019.8741773
Regular:

To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with... View More

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