IEEE - Institute of Electrical and Electronics Engineers, Inc. - Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology

2019 IEEE International Reliability Physics Symposium (IRPS)

Author(s): L. Xu ; J. Cao ; B. L. Bhuva ; I. Chatterjee ; S. -J. Wen ; R. Wong ; L. W. Massengill
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2019
Conference Location: Monterey, CA, USA, USA
Conference Date: 31 March 2019
Page(s): 1 - 5
ISBN (Electronic): 978-1-5386-9504-3
ISSN (Electronic): 1938-1891
DOI: 10.1109/IRPS.2019.8720514
Regular:

Triple-well designs provide excellent noise isolation in mixed-signal circuits. But the presence of deep-n-well significantly affects Single-Event (SE) response of these circuits. Comparison of... View More

Advertisement