IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 40-nm CMOS 7-b 32-GS/s SAR ADC with Background Channel Mismatch Calibration

Author(s): Dong-Shin Jo ; Ba-Ro-Saim Sung ; Min-Jae Seo ; Woo-Cheol Kim ; Seung-Tak Ryu
Sponsor(s): IEEE Circuits and Systems Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1
ISSN (Electronic): 1558-3791
ISSN (Paper): 1549-7747
DOI: 10.1109/TCSII.2019.2916913
Regular:

This brief presents a 7-b 32-GS/s SAR ADC using a massive time-interleaving (TI) architecture. For low-skew multi-phase clocks, generation utilizing a delay-locked loop (DLL) phase-detector (PD)... View More

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