IEEE - Institute of Electrical and Electronics Engineers, Inc. - Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance

Author(s): Francisco Candel ; Alejandro Valero ; Salvador Petit ; Julio Sahuquillo
Sponsor(s): IEEE Comput. Soc. Tech. Committee on Distributed Process
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1
ISSN (CD): 2326-3814
ISSN (Electronic): 1557-9956
ISSN (Paper): 0018-9340
DOI: 10.1109/TC.2019.2907591
Regular:

To support the massive amount of memory accesses that GPGPU applications generate, GPU memory hierarchies are becoming more and more complex, and the Last Level Cache (LLC) size considerably... View More

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