IEEE - Institute of Electrical and Electronics Engineers, Inc. - Marker Layout for Optimizing the Overlay Alignment in a Photolithography Process

Author(s): Ki Bum Lee ; Chang Ouk Kim
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1
ISSN (Electronic): 1558-2345
ISSN (Paper): 0894-6507
DOI: 10.1109/TSM.2019.2907790
Regular:

In the photolithography process of wafer fabrication, a mask pattern is transferred to a wafer in a layer-by-layer fashion, and the pattern alignment of adjacent layers is critical to the wafer... View More

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