IEEE - Institute of Electrical and Electronics Engineers, Inc. - An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC

Author(s): Benjamin T. Reyes ; Laura Biolato ; Agustin C. Galetto ; Leandro Passetti ; Fredy Solis ; Mario R. Hueda
Sponsor(s): IEEE Circuits and Systems Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1 - 13
ISSN (Electronic): 1558-0806
ISSN (Paper): 1549-8328
DOI: 10.1109/TCSI.2019.2901795
Regular:

An energy-efficient sampling architecture for time interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The architecture avoids the use of... View More

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